1. Field of the Invention
The present invention relates to a surface-mount semiconductor device, and more specifically relates to a semiconductor device such as, for example, a CSP (Chip Size Package) or a BGA (Ball Grid Array), of a kind having a plurality of bump electrodes.
2. Description of the Related Art
A conventional semiconductor device 100 comprising a plurality of bump electrodes 101 is shown in a side view in FIG. 8A and in a bottom plan view in FIG. 8B (the bottom being on the side on which the bump electrodes 101 can be seen). As shown in these figures, the bump electrodes 101 are typically arrayed in a matrix pattern. The actual number of bump electrodes varies according to the electrical functions and characteristics of the IC chip of which they are part, but commonly ranges from approximately ten to as many as several hundred.
The electrode contacts of an IC chip sealed in a semiconductor device are connected to proximally positioned bump electrodes according to the bump electrode arrangement. Not all of the bump electrodes are used for supplying power to the IC chip or for exchanging signals and data. As a result, the bump electrodes include both signal pins, which are electrically connected to one of the chip layers, and pins that are not used by the IC chip and to which, therefore, no connection is necessary (referred to as NC or "no connection" pins below). The signal pins and NC pins are also randomly arranged, that is, the signal pins and NC pins are not necessarily grouped in one or more clusters of like pins.
The minimum pitch between bump electrodes in a typical matrix pattern is usually about 0.5 mm, and the minimum diameter of the bump electrodes is approximately 0.2 to 0.3 mm. The smallest width and pitch of the lines that can be provided on a circuit board is therefore approximately 0.2 mm. It is therefore only possible to pass one line between bump electrodes, and NC pins 110a to 110h are randomly dispersed as shown in FIG. 8B according to the arrangement of the electrode contacts of the IC chip.
When the NC pins are arranged around the periphery of the semiconductor device using a different method as described in Japanese Laid-open Patent Publication H6-216271, it is extremely difficult to design a line pattern for connections to a plurality of signal pin bump electrodes positioned inside of this peripheral group of NC pins on a single layer circuit board. Multilayered circuit boards, through-hole wiring, and other design techniques have therefore been used to facilitate wiring to a plurality of bump electrodes in such an inside group.
FIG. 9 is a section view through line IX-IX' in FIG. 8B showing the above-described semiconductor device 100 mounted to a two-layer circuit board comprising layers 102 and 103. As shown in the figure, bump electrodes 120 and 125 at the outside corners of the semiconductor device 100 are connected to lines 104 and 107 on the surface of the first layer 102. Bump electrodes 121 and 124 in the first row inside the outside bump electrodes 120 and 125 are connected through vias 110 and 113 to lines 105 and 108 on the top surface of the second layer 103 as seen in FIG. 9. The inner-most bump electrodes 122 and 123 are then connected to lines 106 and 109 on the back (bottom) of the second layer 103 by way of through-vias 111 and 112.
While this design method enables bump electrode connection as described above, design methods using multiple layers 102 and 103 and vias require more design time than methods using single-layer circuit boards, and result in a more complex structure and higher cost.
Therefore, to simplify the structure, design, and reduce the cost of circuit boards used with semiconductor devices having bump electrodes, there is a need for a semiconductor device having bump electrodes whereby mounting to a circuit board is easier.